1. Field of the Invention
The invention relates generally to phase locked loops (PLLs). Embodiments of the invention relate to PLLs useful in synthesizing frequencies including fractional-N synthesizers.
2. Description of the Related Art
PLLs are commonly used to produce a precise, stable frequency. The basic elements of a PLL include a reference frequency source, a voltage controlled oscillator (VCO), a frequency divider, a phase detector and a loop filter. The output of the VCO is applied to the frequency divider and the output of the frequency divider is applied to the phase detector. The reference frequency is applied as the other input of the phase detector. The phase detector output is proportional to the difference in phase between the two input signals. The output of the phase detector is applied to the loop filter and the output of the loop filter is the input of the VCO.
One type of PLL is referred to as a fractional-N loop or synthesizer. See, e.g., Phase-Locked Loops, Best, Roland E., McGraw-Hill Book Company, 1984, p. 227-229. In a fractional-N synthesizer, the output frequency (f.sub.out) is equal to N.F (f.sub.ref), where N is the integer part and F is the fractional part. A block diagram of a fractional-N syntnesizer is shown in FIG. 1A. This synthesizer includes the basic PLL elements of a VCO 16, a frequency divider (divide N/N+1) 18, which in this case is programmable, and a phase detector 12. This synthesizer also includes an accumulator 21, a digital to analog converter 19 and a summing circuit 13.
The reference frequency (f.sub.ref) is applied to one input of the phase detector 12. The output of the divider 18 is applied to the other input of the phase detector 12. The accumulator 21 receives f.sub.ref as its clocking signal and provides a carry or overflow signal to the divider 18. The carry signal causes the divider 18 to switch from divide by N to divide by N+1. The output of the accumulator 21 is provided to the digital to analog converter 19. The digital to analog converter 19 converts the input to an analog signal which is provided as an input to the summing circuit 13. The other input of the summing circuit 13 is the output of the phase detector 12. The output of the summing circuit 13, the sum of the two input signals, is provided to the loop filter 14. The output of the loop filter 14 is provided to the VCO 16. The output of the VCO 16 is applied to the divider 18.
This circuit is capable of synthesizing frequencies which are a fractional multiple of the reference frequency (f.sub.ref). For example, if a division ratio of 4.25 is desired, that can be accomplished by the fractional-N divider 18 dividing by 4 in 3 cycles of each group of 4 cycles (modulo 4) and dividing by 5 in the remaining cycle, wherein a "cycle" is one period of f.sub.ref. Therefore, over 4 cycles, f.sub.out =4.25 (f.sub.ref).
FIG. 1B is a timing diagram of selected signals of the conventional fractional-N synthesizer circuit shown in FIG. 1A with regard to the specific example, wherein f.sub.out =4.25 f.sub.ref. We begin in the state where the output frequency f.sub.out is already 4.25 times f.sub.ref. The divider 18 has been programmed for N=4. The accumulator 21 has been programmed to generate a "carry" signal at every fourth cycle. During the time intervals T.sub.1 -T.sub.4, f.sub.out, has 17 cycles and f.sub.ref has 4 cycles. Each time interval T equals one period of f.sub.ref. During the time interval T.sub.1, the fractional-N divider 18 divides the signal f.sub.out by 4. In the second time period T.sub.2 and third time period T.sub.3, the divider 18 again divides the signal f.sub.out, by 4. At the beginning of the fourth time period, T.sub.4, the accumulator generates the carry signal which causes the divider to divide by N+1, in this example N+1=5. Therefore, the signal f.sub.out is divided by five during T.sub.4. As can be seen in FIG. 1B, the phase detector 12 detects a negative phase error in time periods T.sub.2, T.sub.3 and T.sub.4 and generates a corresponding output. However, that output is canceled by the output of the digital to analog converter 19 which converts the output of the accumulator 21 to an analog signal which is equal and opposite to the output of the phase detector 12. The output signal of the digital to analog converter 19 is combined with the output of the phase detector 12 by the summing circuit 13 and the two signals effectively cancel each other.
A conventional fractional-N synthesizing, such as shown in FIG. 1A, call provide an effective method for reducing spurs when combined with a sample and hold phase detector. However, that approach has been found not to be effective or efficient when used with phase/frequency detectors and charge pump PLLs. Therefore, there is a need for a method and apparatus for reducing spurs that can be effectively and efficiently used with phase/frequency detectors in charge pump PLLs.